Memory cell

ABSTRACT

A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively.

This application is a reissue application of U.S. Pat. No. 8,879,305.

This application is a continuation of U.S. patent application Ser. No.13/328,685, filed on Dec. 16, 2011, entitled “Memory Cell,” now U.S.Pat. No. 8,625,334, which application is hereby incorporated herein byreference in its entirety.

BACKGROUND

Static random access memory (SRAM) is commonly used in integratedcircuits. SRAM cells have the advantageous feature of holding datawithout a need for refreshing. SRAM cells may include different numbersof transistors, and are often referred to by the number of transistors,for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, andthe like. The transistors typically form a data latch for storing a bit.Additional transistors may be added to control access to thetransistors. SRAM cells are typically arranged as an array having rowsand columns. Each row of the SRAM cells is connected to a word line,which determines whether the current SRAM cell is selected or not. Eachcolumn of the SRAM cells is connected to a bit line (or a pair ofcomplementary bit lines), which is used for writing a bit into, orreading a bit from, the SRAM cell.

Recent advances in finFET transistor technology have made advanced SRAMcells using finFET transistors possible. In contrast to the prior planarMOS transistor, which has a channel formed at the surface of asemiconductor substrate, a finFET has a three dimensional channelregion. In the finFET, the channel for the transistor is formed on thesides, and sometimes also the top, of a “fin” of semiconductor material.The gate, typically a polysilicon or metal gate, extends over the finand a gate dielectric is disposed between the gate and the fin. Thethree-dimensional shape of the finFET channel region allows for anincreased gate width without increased silicon area even as the overallscale of the devices is reduced with semiconductor process scaling, andin conjunction with a reduced gate length, providing a reasonablechannel width characteristic at a low silicon area cost.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present embodiments, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a single port static random access memory(SRAM) bit cell according to an embodiment;

FIG. 2 is an array of bit cells, one example of a bit cell beingdepicted in FIG. 1, according to an embodiment;

FIG. 3 is an example of a four bit cell column comprising bit cells inFIG. 1 according to an embodiment;

FIGS. 4A and 4B are example bit cell layouts for the bit cell in FIG. 1according to embodiments;

FIG. 5 is an example 2×2 array of bit cells with each bit cell using thebit cell layout of FIG. 4A according to an embodiment;

FIGS. 6A and 6B are a first example of metallization patterns for thebit cell layouts in FIG. 4A according to an embodiment;

FIGS. 7A and 7B are a second example of metallization patterns for thebit cell layouts in FIG. 4A according to an embodiment;

FIGS. 8A and 8B are a third example of metallization patterns for thebit cell layouts in FIG. 4A according to an embodiment;

FIGS. 9A and 9B are a fourth example of metallization patterns for thebit cell layouts in FIG. 4A according to an embodiment;

FIG. 10 is a circuit diagram of a dual port SRAM bit cell according toan embodiment;

FIG. 11 is an array of bit cells, one example of a bit cell beingdepicted in FIG. 10, according to an embodiment;

FIG. 12 is an example of a four bit cell column comprising bit cells inFIG. 10 according to an embodiment;

FIG. 13 is an example bit cell layout for the bit cell in FIG. 10according to an embodiment;

FIG. 14 is an example 2×2 array of bit cells with each bit cell usingthe bit cell layout of FIG. 13 according to an embodiment;

FIGS. 15A and 15B are an example of metallization patterns for the bitcell layout in FIG. 13 according to an embodiment;

FIG. 16 is a circuit diagram of a two port SRAM bit cell according to anembodiment;

FIG. 17 is an array of bit cells, one example of a bit cell beingdepicted in FIG. 16, according to an embodiment;

FIG. 18 is an example of a four bit cell column comprising bit cells inFIG. 16 according to an embodiment;

FIG. 19 is an example bit cell layout for the bit cell in FIG. 16according to an embodiment;

FIG. 20 is an example 2×2 array of bit cells with each bit cell usingthe bit cell layout of FIG. 19 according to an embodiment;

FIGS. 21A and 21B are an example of metallization patterns for the bitcell layout in FIG. 19 according to an embodiment;

FIG. 22 is a memory layout according to an embodiment; and

FIGS. 23 through 31 are a method of forming a memory array comprisingfin field effect transistors (finFETs) according to an embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detailbelow. It should be appreciated, however, that the present disclosureprovides many applicable inventive concepts that can be embodied in awide variety of specific contexts. The specific embodiments discussedare merely illustrative of specific ways to make and use the disclosedsubject matter, and do not limit the scope of the different embodiments.

Embodiments will be described with respect to a specific context, namelya memory cell, such as a static random access memory (SRAM) cell. Otherembodiments may also be applied, however, to other circuits and layoutsof circuits where a greater uniformity of the layout is desired.Throughout the various views and illustrative embodiments, likereference numbers are used to designate like elements.

FIG. 1 illustrates a circuit diagram of a single port SRAM bit cellaccording to an embodiment. The cell includes pull-up transistors PU1and PU2, pull-down transistors PD1 and PD2, pass-gate transistors PG1and PG2, and isolation transistors IS1 and IS2. As show in the circuitdiagram, transistors PU1, PU2, IS1, and IS2 are p-type transistors, suchas planar p-type field effect transistors (PFETs) or p-type fin fieldeffect transistors (finFETs), and transistors PD1, PD2, PG1, and PG2 aren-type transistors, such as planar n-type field effect transistors(NFETs) or n-type finFETs.

The drains of pull-up transistors PU1 and pull-down transistor PD1 arecoupled together, and the drains of pull-up transistor PU2 and pull-downtransistor PD2 are coupled together. Transistors PU1 and PD1 arecross-coupled with transistors PU2 and PD2 to form a data latch. Thegates of transistors PU1 and PD1 are coupled together and to the drainsof transistors PU2 and PD2, and the gates of transistors PU2 and PD2 arecoupled together and to the drains of transistors PU1 and PD1. Sourcesof the pull-up transistors PU1 and PU2 are coupled to power voltage Vdd,and the sources of the pull-down transistors PD1 and PD2 are coupled toa ground voltage Vss.

Storage node N1 of the data latch is coupled to bit line BL throughpass-gate transistor PG1, and storage node N2 is coupled tocomplementary bit line BLB through pass-gate transistor PG2. Storagenodes N1 and N2 are complementary nodes that are often at opposite logiclevels (logic high or logic low). Gates of pass-gate transistors PG1 andPG2 are coupled to a word line WL. The source and gate of the isolationtransistor IS1 are coupled together and to the storage node N1, and thesource and gate of the isolation transistor IS2 are coupled together andto the storage node N2. Drains of the isolation transistors IS1 and IS2are depicted as floating, but may be coupled to respective isolationtransistors in adjacent cells, as will be discussed.

FIG. 2 is an array of bit cells, one example of a bit cell beingdepicted in FIG. 1. The array has n number of columns and m number ofrows. The array comprises m×n number of bit cells, with m number of bitcells in each column and n number of bit cells in each row. Each columnhas a bit line BL-n and a complementary bit line BLB-n, and each row hasa word line WL-m. As a person having ordinary skill in the art willreadily understand, a selection of a word line and a bit line will readfrom or write to a bit cell at the intersection of the selected wordline and bit line. A power line Vdd and a ground line Vss are depictedin each column, but these lines may be in each row or in a combinationof a row and a column, as will be discussed later.

FIG. 3 is an example of a four bit cell column according to anembodiment. The column, as depicted, comprises four bit cells C1, C2,C3, and C4, each of which being the bit cell in FIG. 1 with boundariesindicated by the dashed lines. The bit line BL and complementary bitline BLB extend through each bit cell C1, C2, C3, and C4, as indicatedin FIG. 2. The drain of the isolation transistor IS1 in each cell iscoupled to the drain of another isolation transistor IS1 in an adjacentcell. For example, the drain of transistor IS1 in bit cell C1 is coupledto the drain of transistor IS1 in bit cell C2, and the drain oftransistor IS1 in bit cell C3 is coupled to the drain of transistor IS1in bit cell C4. Further, the drain of the isolation transistor IS2 ineach cell is coupled to the drain of another isolation transistor IS2 inan adjacent cell. For example, the drain of transistor IS2 in bit cellC2 is coupled to the drain of transistor IS2 in bit cell C3. A personhaving ordinary skill in the art will readily understand that the drainsof the isolation transistors IS2 in bit cells C1 and C4 can be coupledto isolation transistors in further adjacent cells, although four cellsare depicted for illustration purposes. Isolation transistors IS1 or IS2in cells at a beginning or end of a column can be coupled to transistorsin dummy cells and/or left in a floating state.

FIGS. 4A and 4B illustrate example bit cell layouts for the bit cell inFIG. 1 according to embodiments. In FIG. 4A, four active areas that makeup the source/drain regions and channel regions of the varioustransistors extend longitudinally parallel across the width of the bitcell. For reference, longitudinal axes of the active areas extend in they-direction of the bit cell. Four gate patterns of the varioustransistors extend longitudinally parallel along the length, e.g., thex-direction, of the bit cell. It should be noted that the terms widthand length and the various directions are used for ease of reference anddo not imply that a cell requires any particular dimensions ororientation. For further ease of reference, the dashed rectangle (asopposed to the two dashed lines intersecting the dashed rectangle)circumscribing the bit cell indicates a boundary of the bit cell.

The dashed lines that intersect the cell indicate boundaries between ap-type well in the substrate and an n-type well in the substrate inwhich respective active areas are formed. The active area of transistorsPG1 and PD1 is formed in a p-type well, as these transistors are n-typetransistors. The two active areas of transistors IS1, PU1, PU2, and IS2are formed in an n-type well, as these transistors are p-typetransistors. The active area of transistors PD2 and PG2 is formed in ap-type well, as these transistors are n-type transistors. As personhaving ordinary skill in the art will readily understand thatsource/drain regions of the active areas of the transistors aregenerally doped an opposite dopant type from that of the well. Forexample, a source/drain region is generally p-type doped when the wellin which the active area is formed is an n-type well.

A single gate pattern is used as the gates of transistors PD1, PU1, andIS2, and another single gate pattern is used as the gates of transistorsPD2, PU2, and IS1. In this manner, each single gate pattern electricallycouples the gates of the respective three transistors. A gate patternfor pass-gate transistor PG1 extends beyond a cell boundary so that thegate pattern can be shared by an adjacent bit cell, as does a gatepattern for pass-gate transistor PG2.

Various contacts couple components in the bit cell. A word line contactWL is coupled to the gate of pass-gate transistor PG1, and another wordline contact WL is coupled to the gate of pass-gate transistor PG2. Abit line contact BL is coupled to the drain of pass-gate transistor PG1,and an complementary bit line contact BLB is coupled to the drain ofpass-gate transistor PG2. A power contact Vdd is coupled to the sourceof pull-up transistor PU1, and another power contact Vdd is coupled tothe source of pull-up transistor PU2. A ground contact Vss is coupled tothe source of pull-down transistor PD1, and another ground contact Vssis coupled to the source of pull-down transistor PD2. A node contact N1couples together the sources of transistors PG1 and IS1 and the drainsof transistors PD1 and PU1, and a node contact N2 couples together thesources of transistors PG2 and IS2 and the drains of transistors PD2 andPU2. A butted contact BC1 couples the source of isolation transistor IS1to the gate of the isolation transistor IS1, and a butted contact BC2couples the source of isolation transistor IS2 to the gate of theisolation transistor IS2.

FIG. 4B is a second example of a bit cell layout. The cell layout ofFIG. 4B is similar to FIG. 4A, and includes transistors in the p-typewells with a double pitch. In this example, a double pitch refersgenerally to a transistor comprising two active areas. In FIG. 4B, twoactive areas extend across the width of the cell in a p-type well toform components of transistors PG1 and PD1, and similarly, two activeareas extend across the width of the cell in a p-type well to formcomponents of transistors PG2 and PD2. Various modifications can be madeto contacts and gates to extend to cover and/or contact appropriatecomponents. By having a double pitch to transistors PG1, PD1, PD2, andPG2, the channel width of each transistor can be effectively doubledthus increasing the driving ability of each transistor. Otherembodiments contemplate various different pitches for varioustransistors.

FIG. 5 depicts an example 2×2 array of bit cells C1, C2, C3, and C4 witheach bit cell using the bit cell layout of FIG. 4A according to anembodiment. It should be noted that the bit cell layout of FIG. 4B orother layouts may be similarly used. For ease of reference, a column isreferred to as being in the y-direction in this example. Thus, bit cellsC1 and C2 are in a first column, and bit cells C3 and C4 are in a secondcolumn. As depicted, adjacent cells in the array are mirror images alonga border between the adjacent cells.

Each active area in a bit cell extends through multiple bit cells in acolumn. In an embodiment, each active area in a bit cell extends throughall of the bit cells in a column. In other embodiments, each active areaextends through less than all of the bit cells in the column. In FIG. 5,the active area for transistors IS2 and PU2 in bit cell C1 extendsthrough bit cell C2 as the active area for transistors PU2 and IS2. Inthis configuration, the drains of the isolation transistors IS2 inadjacent bit cells C1 and C2 are coupled together (such as depicted inFIG. 3 between bit cells C2 and C3) because the drains share a commonnode along the same active area. Similarly, the active area fortransistors IS2 and PU2 in bit cell C3 extends through bit cell C4 asthe active area for transistors PU2 and IS2. Although not illustrated,each of the active areas of isolation transistors IS1 in each bit cellextends into an adjacent bit cell to be the active area of respectiveisolation transistors IS1 in the adjacent bit cell, thereby forming thecoupling between isolation transistors IS1 in adjacent bit cells, asdepicted in FIG. 3.

In operation, the bit cells in FIGS. 1 through 5 generally operate as aconventional single port SRAM cell operates. When write operations areperformed, pass-gate transistors PG1 and PG2 are turned on, and avoltage to which the bit line BL and the complementary bit line BLB aredriven will be sensed through the pass-gate transistors PG1 and PG2 bythe cross-coupled transistors PU1, PU2, PD1, and PD2. The cross-coupledtransistors PU1, PU2, PD1, and PD2 drive the storage nodes N1 and N2 toa high or low state based on the sensing (with the storage nodes N1 andN2 being complementary of each other). The data is thus written into thebit cell through bit lines BL and BLB. Conversely, when read operationsare performed, pass-gate transistors PG1 and PG2 are turned on, and thedata is read onto the bit line BL and complementary bit line BLB throughthe pass-gate transistors PG1 and PG2.

The isolation transistors IS1 and IS2 may have a negligible effect onthe operation of the bit cell. When the node to which the source andgate of the isolation transistor IS1 or IS2 is coupled is at a highvoltage, e.g., a logic high, the voltage at the gate of the isolationtransistor IS1 or IS2 is also high, and the isolation transistor IS1 orIS2 will be in an “off” state. When the node is at a low voltage, e.g.,a logic low, the voltage at the gate will also be low, and the isolationtransistor IS1 or IS2 will be in an “on” state. However, because thevoltage at the source is also low, such as coupled to ground, no currentwill flow away from the node through the isolation transistor IS1 orIS2. In some instances, a small amount of leakage may flow through theisolation transistor IS1 or IS2 when the voltage at the node isswitched, e.g., from low to high and vice versa. With fast switchingtimes and/or low voltages, the leakage current can be very small andnegligible.

By having the bit cells in the configuration in FIG. 5, active areas canbe uniformly spaced and can uniformly extend throughout an array of bitcells. For example, the spacing between active areas in the x-directioncan be uniform, although in embodiments comprising double pitch or othermultiple pitch transistors, the spacing may not be uniform, particularlybecause of the spacing between the active areas of the multiple pitchtransistors. Further, the active areas can extend longitudinally acrossmultiple bit cells without being interrupted by an isolation area. Thisconfiguration can improve the uniformity of an array layout, andthereby, avoid lithography problems that may arise in forming the activeareas, particularly fins for finFET active areas and in small technologynodes.

FIG. 6A through 8B illustrate various examples of metallization patternsfor the bit cell layouts in FIGS. 4A and 4B. The dashed rectangles inthese figures indicate a boundary of the bit cell that corresponds tothe boundary shown in FIGS. 4A and 4B. These are example patterns, and aperson having ordinary skill in the art will readily appreciate variousmodifications to the examples or different patterns that arecontemplated within the scope of embodiments.

FIG. 6A is a first metallization pattern M1 in a first inter-metaldielectric layer IMD1, and FIG. 6B is a second metallization pattern M2in a second inter-metal dielectric layer IMD2 overlying the firstinter-metal dielectric layer IMD1. In FIG. 6A, the first metallizationpattern M1 includes a bit line trace BL, a power trace Vdd, and acomplementary bit line trace BLB, each extending substantiallylongitudinally in the y-direction, which in the context of FIG. 5 isalong a column. The first metallization pattern M1 further includes fourlanding pads L1, L2, L3, and L4. Although not expressly shown, a personhaving ordinary skill in the art will readily understand that viasextend below and from the first metallization pattern M1 to therespective contacts shown in the bit cell layouts in FIGS. 4A and 4B. InFIG. 6B, the second metallization pattern M2 includes a word line traceWL and two ground traces Vss, each extending longitudinally in thex-direction, which in the context of FIG. 5 is along a row. Vias V1, V2,V3, and V4 extend below and from the second metallization pattern M2 torespective landing pads L1, L2, L3, and L4 in the first metallizationpattern M1. Each of the traces in FIGS. 6A and 6B can transversemultiple cells in the respective directions in which the traceslongitudinally extend.

FIG. 7A is a first metallization pattern M1 in a first inter-metaldielectric layer IMD1, and FIG. 7B is a second metallization pattern M2in a second inter-metal dielectric layer IMD2 overlying the firstinter-metal dielectric layer IMD1. In FIG. 7A, the first metallizationpattern M1 includes a first ground trace Vss1, a bit line trace BL, apower trace Vdd, a complementary bit line trace BLB, and a second groundtrace Vss2, each extending longitudinally in the y-direction, which inthe context of FIG. 5 is along a column. The first metallization patternM1 further includes two landing pads L1 and L2. Although not expresslyshown, a person having ordinary skill in the art will readily understandthat vias extend below and from the first metallization pattern M1 tothe respective contacts shown in the bit cell layouts in FIGS. 4A and4B. In FIG. 7B, the second metallization pattern M2 includes a word linetrace WL extending longitudinally in the x-direction, which in thecontext of FIG. 5 is along a row. Vias V1 and V2 extend below and fromthe second metallization pattern M2 to respective landing pads L1 and L2in the first metallization pattern M1. Each of the traces in FIGS. 7Aand 7B can transverse multiple cells in the respective directions inwhich the traces longitudinally extend.

FIG. 8A is a first metallization pattern M1 in a first inter-metaldielectric layer IMD1, and FIG. 8B is a second metallization pattern M2in a second inter-metal dielectric layer IMD2 overlying the firstinter-metal dielectric layer IMD1. In FIG. 8A, the first metallizationpattern M1 includes a word line trace WL extending longitudinally in thex-direction, which in the context of FIG. 5 is along a row. The firstmetallization pattern M1 further includes six landing pads L1, L2, L3,L4, L5, and L6. Although not expressly shown, a person having ordinaryskill in the art will readily understand that vias extend below and fromthe first metallization pattern M1 to the respective contacts shown inthe bit cell layouts in FIGS. 4A and 4B. In FIG. 8B, the secondmetallization pattern M2 includes a first ground trace Vss1, a bit linetrace BL, a power trace Vdd, a complementary bit line trace BLB, and asecond ground trace Vss2, each extending longitudinally in they-direction, which in the context of FIG. 5 is along a column. Vias V1,V2, V3, V4, V5, and V6 extend below and from the second metallizationpattern M2 to respective landing pads L1, L2, L3, L4, L5, and L6 in thefirst metallization pattern M1. Each of the traces in FIGS. 8A and 8Bcan transverse multiple cells in the respective directions in which thetraces longitudinally extend.

FIG. 9A is a first metallization pattern M1 in a first inter-metaldielectric layer IMD1, and FIG. 9B is a second metallization pattern M2in a second inter-metal dielectric layer IMD2 overlying the firstinter-metal dielectric layer IMD1. In FIG. 9A, the first metallizationpattern M1 includes a first ground trace Vss1, a bit line trace BL, apower trace Vdd, a complementary bit line trace BLB, and a second groundtrace Vss2, each extending longitudinally in the y-direction, which inthe context of FIG. 5 is along a column. The first metallization patternM1 further includes two landing pads L1 and L2. Although not expresslyshown, a person having ordinary skill in the art will readily understandthat vias extend below and from the first metallization pattern M1 tothe respective contacts shown in the bit cell layouts in FIGS. 4A and4B. In FIG. 9B, the second metallization pattern M2 includes a word linetrace WL and a ground power mesh trace VssPM, each extendinglongitudinally in the x-direction, which in the context of FIG. 5 isalong a row. Vias V1 and V4 extend below and from the secondmetallization pattern M2 to respective landing pads L1 and L2 in thefirst metallization pattern M1. Vias V2 and V3 extend below and from thesecond metallization pattern M2 to couple the first ground trace Vss1and the second ground trace Vss2, respectively. The ground power meshtrace VssPM can be used to aid in preventing the first ground trace Vss1and the second ground trace Vss2 from having a voltage differencebetween those traces. Each of the traces in FIGS. 9A and 9B cantransverse multiple cells in the respective directions in which thetraces longitudinally extend.

FIG. 10 illustrates a circuit diagram of a dual port SRAM bit cellaccording to an embodiment. The cell includes pull-up transistors PU1and PU2, pull-down transistors PD1 and PD2, pass-gate transistors PG1,PG2, PG3, and PG4, and isolation transistors IS1 and IS2. As show in thecircuit diagram, transistors PU1, PU2, IS1, and IS2 are p-typetransistors, such as planar PFETs or p-type finFETs, and transistorsPD1, PD2, PG1, PG2, PG3, and PG4 are n-type transistors, such as planarNFETs or n-type finFETs.

The drains of pull-up transistor PU1 and pull-down transistor PD1 arecoupled together, and the drains of pull-up transistor PU2 and pull-downtransistor PD2 are coupled together. Transistors PU1 and PD1 arecross-coupled with transistors PU2 and PD2 to form a data latch. Thegates of transistors PU1 and PD1 are coupled together and to the drainsof transistors PU2 and PD2, and the gates of transistors PU2 and PD2 arecoupled together and to the drains of transistors PU1 and PD1. Sourcesof the pull-up transistors PU1 and PU2 are coupled to power voltage Vdd,and the sources of the pull-down transistors PD1 and PD2 are coupled toa ground voltage Vss.

Storage node N1 of the data latch is coupled to a first bit line ABLthrough pass-gate transistor PG1 and to a second bit line BBL throughpass-gate transistor PG3, and storage node N2 is coupled to acomplementary first bit line ABLB through pass-gate transistor PG2 andto a complementary second bit line BBLB through pass-gate transistorPG4. Storage nodes N1 and N2 are complementary nodes that are often atopposite logic levels (logic high or logic low). Gates of pass-gatetransistors PG1 and PG2 are coupled to a first word line AWL, and gatesof pass-gate transistors PG3 and PG4 are coupled to a second word lineBWL. The source and gate of the isolation transistor IS1 are coupledtogether and to the storage node N1, and the source and gate of theisolation transistor IS2 are coupled together and to the storage nodeN2. Drains of the isolation transistors IS1 and IS2 are depicted asfloating, but may be coupled to respective isolation transistors inadjacent cells, as will be discussed.

FIG. 11 is an array of bit cells, one example of a bit cell beingdepicted in FIG. 10. The array has n number of columns and m number ofrows. The array comprises m×n number of bit cells, with m number of bitcells in each column and n number of bit cells in each row. Each columnhas a first bit line ABL-n, a complementary first bit line ABLB-n, asecond bit line BBL-n, and a complementary second bit line BBLB-n, andeach row has a first word line AWL-m and a second word line BWL-m. As aperson having ordinary skill in the art will readily understand, aselection of a word line and a bit line will read from or write to a bitcell at the intersection of the selected word line and bit line. A powerline Vdd and a ground line Vss are depicted in each column, but theselines may be in each row or in a combination of a row and a column.

FIG. 12 is an example of a four bit cell column according to anembodiment. The column, as depicted, comprises four bit cells C1, C2,C3, and C4, each of which being the bit cell in FIG. 10 with boundariesindicated by the dashed lines. The first bit line ABL, complementaryfirst bit line ABLB, the second bit line BBL, and complementary secondbit line BBLB extend through each bit cell C1, C2, C3, and C4, asindicated in FIG. 11. The drain of the isolation transistor IS1 in eachcell is coupled to the drain of another isolation transistor IS1 in anadjacent cell. For example, the drain of isolation transistor IS1 in bitcell C1 is coupled to the drain of isolation transistor IS1 in bit cellC2, and the drain of isolation transistor IS1 in bit cell C3 is coupledto the drain of isolation transistor IS1 in bit cell C4. Further, thedrain of the isolation transistor IS2 in each cell is coupled to thedrain of another isolation transistor IS2 in an adjacent cell. Forexample, the drain of isolation transistor IS2 in bit cell C2 is coupledto the drain of isolation transistor IS2 in bit cell C3. A person havingordinary skill in the art will readily understand that the drains of theisolation transistors IS2 in bit cells C1 and C4 can be coupled toisolation transistors in further adjacent cells, although four cells aredepicted for illustration purposes. Isolation transistors IS1 or IS2 incells at a beginning or end of a column can be coupled to transistors indummy cells and/or left in a floating state.

FIG. 13 illustrates an example bit cell layout for the bit cell in FIG.10 according to an embodiment. In FIG. 13, ten active areas that make upthe source/drain regions and channel regions of the various transistorsextend longitudinally parallel across the width of the bit cell. Forreference, longitudinal axes of the active areas extend in they-direction of the bit cell. Six gate patterns of the varioustransistors extend longitudinally parallel along the length, e.g., thex-direction, of the bit cell. It should be noted that the terms widthand length and the various directions are used for ease of reference anddo not imply that a cell requires any particular dimensions ororientation. For further ease of reference, the dashed rectangle (asopposed to the two dashed lines intersecting the dashed rectangle)circumscribing the bit cell indicates a boundary of the bit cell.

The dashed lines that intersect the cell indicate boundaries between ap-type well in the substrate and an n-type well in the substrate inwhich respective active areas are formed. The four active areas oftransistors PG1, PG3, and PD1 are formed in a p-type well, as thesetransistors are n-type transistors. The two active areas of transistorsIS1, PU1, PU2, and IS2 are formed in an n-type well, as thesetransistors are p-type transistors. The four active areas of transistorsPG2, PG4, and PD2 are formed in a p-type well, as these transistors aren-type transistors.

As depicted the pull-down transistors PD1 and PD2 are each essentially aquadruple pitch transistor, with each transistor comprising two parallelcoupled double pitch transistors PD1-1 and PD1-2 (for transistor PD1)and PD2-1 and PD2-1 (for transistor PD2). Further the pass-gatetransistors PG1, PG2, PG3, and PG4 are each double pitch transistors.FIG. 13 is an example layout, and various transistors can be single ormultiple pitch transistors.

A single gate pattern is used as the gates of transistors PD1, PU1, andIS2, and another single gate pattern is used as the gates of transistorsPD2, PU2, and IS1. In this manner, each single gate pattern electricallycouples the gates of the respective three transistors. A gate patternfor pass-gate transistor PG1 extends beyond a cell boundary so that thegate pattern can be shared by an adjacent bit cell, as does a gatepattern for pass-gate transistor PG2. Each of pass-gate transistors PG3and PG4 has a gate pattern that does not extend to another transistorand remains internal to the bit cell.

Various contacts couple components in the bit cell. A first word linecontact AWL is coupled to the gate of pass-gate transistor PG1, andanother first word line contact AWL is coupled to the gate of pass-gatetransistor PG2. A second word line contact BWL is coupled to the gate ofpass-gate transistor PG3, and another second word line contact BWL iscoupled to the gate of pass-gate transistor PG4. A first bit linecontact ABL is coupled to the drain of pass-gate transistor PG1, and acomplementary first bit line contact ABLB is coupled to the drain ofpass-gate transistor PG2. A second bit line contact BBL is coupled tothe drain of pass-gate transistor PG3, and a complementary second bitline contact BBLB is coupled to the drain of pass-gate transistor PG4. Apower contact Vdd is coupled to the source of pull-up transistor PU1,and another power contact Vdd is coupled to the source of pull-uptransistor PU2. A ground contact Vss is coupled to the source ofpull-down transistor PD1 (or the sources of transistors PD1-2 and PD1-1with the quadruple pitch transistor, as depicted), and another groundcontact Vss is coupled to the source of pull-down transistor PD2 (or thesources of transistors PD2-2 and PD2-1 with the quadruple pitchtransistor, as depicted). A node contact N1 couples together the sourcesof transistors PG1, PG3, and IS1 and drains of transistors PD1 (ordrains of transistors PD1-2 and PD1-1) and PU1, and a node contact N2couples together the sources of transistors PG2, PG4, and IS2 and drainsof transistors PD2 (or drains of transistors PD2-2 and PD2-1) and PU2. Abutted contact BC1 couples the source of isolation transistor IS1 to thegate of the isolation transistor IS1, and a butted contact BC2 couplesthe source of isolation transistor IS2 to the gate of the isolationtransistor IS2.

FIG. 14 depicts an example 2×2 array of bit cells C1, C2, C3, and C4,with each bit cell using the bit cell layout of FIG. 13 according to anembodiment. It should be noted that the bit cell layout of FIG. 13 orother layouts may be similarly used. For ease of reference, a column isreferred to as being in the y-direction in this example. Thus, bit cellsC1 and C2 are in a first column, and bit cells C3 and C4 are in a secondcolumn. As depicted, adjacent cells in the array are mirror images alonga border between the adjacent cells.

Each active area in a bit cell extends through multiple bit cells in acolumn. In an embodiment, each active area in a bit cell extends throughall of the bit cells in a column. In other embodiments, each active areaextends through less than all of the bit cells in the column. In FIG.14, the active area for transistors IS1 and PU1 in bit cell C1 extendsthrough bit cell C2 as the active area for transistors PU1 and IS1. Inthis configuration, the drains of the isolation transistors IS1 inadjacent bit cells C1 and C2 are coupled together (such as depicted inFIG. 12 between bit cells C1 and C2) because the drains share a commonnode along the same active area. Similarly, the active area fortransistors IS1 and PU1 in bit cell C3 extends through bit cell C4 asthe active area for transistors PU1 and IS1. Although not illustrated,each of the active areas of isolation transistors IS2 in each bit cellextends into an adjacent bit cell to be the active area of respectiveisolation transistors IS2 in the adjacent bit cell, thereby forming thecoupling between isolation transistors IS2 in adjacent bit cells, asdepicted in FIG. 12.

In operation, the bit cells in FIGS. 10 through 14 generally operate asa conventional dual port SRAM cell operates. When write operations areperformed on a first port, pass-gate transistors PG1 and PG2 are turnedon using the first word line AWL, and a voltage to which the first bitline ABL and the complementary first bit line ABLB are driven will besensed through the pass-gate transistors PG1 and PG2 by thecross-coupled transistors PU1, PU2, PD1, and PD2. When write operationsare performed on a second port, pass-gate transistors PG3 and PG4 areturned on using the second word line BWL, and a voltage to which thesecond bit line BBL and the complementary second bit line BBLB aredriven will be sensed through the pass-gate transistors PG3 and PG4 bythe cross-coupled transistors PU1, PU2, PD1, and PD2. The cross-coupledtransistors PU1, PU2, PD1, and PD2 drive the storage nodes N1 and N2 toa high or low state based on the sensing (with the storage nodes N1 andN2 being complementary of each other). The data is thus written into thebit cell through bit lines ABL, ABLB, BBL, and BBLB. Conversely, whenread operations are performed through a first port, pass-gatetransistors PG1 and PG2 are turned on by the first word line AWL, andthe data is read onto the first bit line ABL and complementary first bitline ABLB through the pass-gate transistors PG1 and PG2. When readoperations are performed through a second port, pass-gate transistorsPG3 and PG4 are turned on by the second word line BWL, and the data isread onto the second bit line BBL and complementary second bit line BBLBthrough the pass-gate transistors PG3 and PG4.

As previously discussed with respect to FIGS. 1 through 5, the isolationtransistors IS1 and IS2 in FIGS. 10 through 14 may have a negligibleeffect on the operation of the bit cell. During operation, currentgenerally may not flow through the isolation transistors IS1 and IS2,and in some instances, a small amount of leakage may flow through theisolation transistor IS1 or IS2 when the voltage at the node isswitched, e.g., from low to high and vice versa. With fast switchingtimes and/or low voltages, the leakage current can be very small andnegligible.

By having the bit cells in the configuration in FIG. 14, active areascan be more uniformly spaced and can uniformly extend throughout anarray of bit cells, as discussed with reference to FIG. 5. Further, theactive areas can extend longitudinally across multiple bit cells withoutbeing interrupted by an isolation area.

FIGS. 15A and 15B illustrate an example of metallization patterns forthe bit cell layout in FIG. 13. The dashed rectangles in these figuresindicate a boundary of the bit cell that corresponds to the boundaryshown in FIGS. 13. These are an example pattern, and a person havingordinary skill in the art will readily appreciate various modificationsto the example or different patterns that are contemplated within thescope of embodiments.

FIG. 15A is a first metallization pattern M1 in a first inter-metaldielectric layer IMD1, and FIG. 15B is a second metallization pattern M2in a second inter-metal dielectric layer IMD2 overlying the firstinter-metal dielectric layer IMD1. In FIG. 15A, the first metallizationpattern M1 includes a first bit line trace ABL, a first ground traceVss1, a second bit line trace BBL, a power trace Vdd, a complementarysecond bit line trace BBLB, a second ground trace Vss2, and a firstcomplementary bit line trace ABLB, each trace extending longitudinallyin the y-direction, which in the context of FIG. 14 is along a column.The first metallization pattern M1 further includes four landing padsL1, L2, L3, and L4. Although not expressly shown, a person havingordinary skill in the art will readily understand that vias extend belowand from the first metallization pattern M1 to the respective contactsshown in the bit cell layout in FIG. 13. In FIG. 15B, the secondmetallization pattern M2 includes a first word line trace AWL and asecond word line trace BWL, each extending longitudinally in thex-direction, which in the context of FIG. 14 is along a row. Vias V1,V2, V3, and V4 extend below and from the second metallization pattern M2to respective landing pads L1, L2, L3, and L4 in the first metallizationpattern M1. Each of the traces in FIGS. 15A and 15B can transversemultiple cells in the respective directions in which the traceslongitudinally extend.

FIG. 16 illustrates a circuit diagram of a two port SRAM bit cellaccording to an embodiment. The cell includes pull-up transistors PU1and PU2, pull-down transistors PD1 and PD2, pass-gate transistors PG1and PG2, a read pass-gate transistor RPG, a read pull-down transistorRPD, and isolation transistors IS1 and IS2. As show in the circuitdiagram, transistors PU1, PU2, IS1, and IS2 are p-type transistors, suchas planar PFETs or p-type finFETs, and transistors PD1, PD2, PG1, PG2,RPD, and RPG are n-type transistors, such as planar NFETs or n-typefinFETs.

The drains of pull-up transistor PU1 and pull-down transistor PD1 arecoupled together, and the drains of pull-up transistor PU2 and pull-downtransistor PD2 are coupled together. Transistors PU1 and PD1 arecross-coupled with transistors PU2 and PD2 to form a data latch. Thegates of transistors PU1 and PD1 are coupled together and to the drainsof transistors PU2 and PD2, and the gates of transistors PU2 and PD2 arecoupled together and to the drains of transistors PU1 and PD1. Sourcesof the pull-up transistors PU1 and PU2 are coupled to power voltage Vdd,and the sources of the pull-down transistors PD1 and PD2 are coupled toa ground voltage Vss.

Storage node N1 of the data latch is coupled to write bit line WBLthrough pass-gate transistor PG1, and storage node N2 is coupled tocomplementary write bit line WBLB through pass-gate transistor PG2.Storage nodes N1 and N2 are complementary nodes that are often atopposite logic levels (logic high or logic low). Gates of pass-gatetransistors PG1 and PG2 are coupled to write word line WWL. The sourceof the read pull-down transistor RPD is coupled to the ground voltageVSS, and the gate of the read pull-down transistor RPD is coupled to thestorage node N1. The drain of the read pull-down transistor RPD iscoupled to the source of the read pass-gate transistor RPG. The gate oftransistor RPG is coupled to a read word line RWL, and the drain oftransistor RPG is coupled to a read bit line RBL. The source and gate ofthe isolation transistor IS1 are coupled together and to the storagenode N1, and the source and gate of the isolation transistor IS2 arecoupled together and to the storage node N2. Drains of the isolationtransistors IS1 and IS2 are depicted as floating, but may be coupled torespective isolation transistors in adjacent cells, as will bediscussed.

FIG. 17 is an array of bit cells, one example of a bit cell beingdepicted in FIG. 16. The array has n number of columns and m number ofrows. The array comprises m×n number of bit cells, with m number of bitcells in each column and n number of bit cells in each row. Each columnhas a write bit line WBL-n, a complementary write bit line WBLB-n, and aread bit line RBL-n, and each row has a write word line WWL-m and a readword line RWL-m. As a person having ordinary skill in the art willreadily understand, a selection of a word line and a bit line will readfrom or write to a bit cell at the intersection of the selected wordline and bit line. A power line Vdd and a ground line Vss are depictedin each column, but these lines may be in each row or in a combinationof a row and a column.

FIG. 18 is an example of a four bit cell column according to anembodiment. The column, as depicted, comprises four bit cells C1, C2,C3, and C4, each of which being the bit cell in FIG. 16 with boundariesindicated by the dashed lines. The write bit line WBL, complementarywrite bit line WBLB, and read bit line RBL extend through each bit cellC1, C2, C3, and C4, as indicated in FIG. 17. The drain of the isolationtransistor IS1 in each cell is coupled to the drain of another isolationtransistor IS1 in an adjacent cell. For example, the drain of isolationtransistor IS1 in bit cell C1 is coupled to the drain of isolationtransistor IS1 in bit cell C2, and the drain of isolation transistor IS1in bit cell C3 is coupled to the drain of isolation transistor IS1 inbit cell C4. Further, the drain of the isolation transistor IS2 in eachcell is coupled to the drain of another isolation transistor IS2 in anadjacent cell. For example, the drain of isolation transistor IS2 in bitcell C2 is coupled to the drain of isolation transistor IS2 in bit cellC3. A person having ordinary skill in the art will readily understandthat the drains of the isolation transistors IS2 in bit cells C1 and C4can be coupled to isolation transistors in further adjacent cells,although four cells are depicted for illustration purposes. Isolationtransistors IS1 or IS2 in cells at a beginning or end of a column can becoupled to transistors in dummy cells and/or left in a floating state.

FIG. 19 illustrates an example bit cell layout for the bit cell in FIG.16 according to an embodiment. In FIG. 19, six active areas that make upthe source/drain regions and channel regions of the various transistorsextend longitudinally parallel across the width of the bit cell. Forreference, longitudinal axes of the active areas extend in they-direction of the bit cell. Five gate patterns of the varioustransistors extend longitudinally parallel along the length, e.g., thex-direction, of the bit cell. It should be noted that the terms widthand length and the various directions are used for ease of reference anddo not imply that a cell requires any particular dimensions ororientation. For further ease of reference, the dashed rectangle (asopposed to the two dashed lines intersecting the dashed rectangle)circumscribing the bit cell indicates a boundary of the bit cell.

The dashed lines that intersect the cell indicate boundaries between ap-type well in the substrate and an n-type well in the substrate inwhich respective active areas are formed. The active area of transistorsPG1 and PD1 is formed in a p-type well, as these transistors are n-typetransistors. The two active areas of transistors IS1, PU1, PU2, and IS2are formed in an n-type well, as these transistors are p-typetransistors. The three active areas of transistors PG2, PD2, RPD, andRPG are formed in a p-type well, as these transistors are n-typetransistors.

As depicted transistors RPD and RPG are double pitch transistors, andthe other transistors are single pitch. FIG. 19 is an example layout,and various transistors can be single or multiple pitch transistors.

A single gate pattern is used as the gates of transistors PD1, PU1, andIS2, and another single gate pattern is used as the gates of transistorsPD2, PU2, IS1, and RPD. In this manner, each single gate patternelectrically couples the gates of the respective transistors. A gatepattern for pass-gate transistor PG1 extends beyond a cell boundary sothat the gate pattern can be shared by an adjacent bit cell, as does agate pattern for read pass-gate transistor RPG. A gate pattern forpass-gate transistor PG2 is internal to the bit cell and does not extendto another transistor.

Various contacts couple components in the bit cell. A write word linecontact WWL is coupled to the gate of pass-gate transistor PG1, andanother write word line contact WWL is coupled to the gate of pass-gatetransistor PG2. A read word line contact RWL is coupled to the gate ofread pass-gate transistor RPG. A write bit line contact WBL is coupledto drain of pass-gate transistor PG1, and a complementary write bit linecontact WBLB is coupled to drain of pass-gate transistor PG2. A read bitline contact RBL is coupled to drain of read pass-gate transistor RPG. Apower contact Vdd is coupled to the source of pull-up transistor PU1,and another power contact Vdd is coupled to the source of pull-uptransistor PU2. A ground contact Vss is coupled to the source ofpull-down transistor PD1, and another ground contact Vss is coupled tothe sources of transistors PD2 and RPD. A node contact N1 couplestogether the sources of transistors PG1 and IS1 and drains oftransistors PD1 and PU1, and a node contact N2 couples together thesources of transistors PG2 and IS2 and drains of transistors PD2 andPU2. A butted contact BC1 couples the source of isolation transistor IS1to the gate of the isolation transistor IS1, and a butted contact BC2couples the source of isolation transistor IS2 to the gate of theisolation transistor IS2.

FIG. 20 depicts an example 2×2 array of bit cells C1, C2, C3, and C4,with each bit cell using the bit cell layout of FIG. 19 according to anembodiment. It should be noted that the bit cell layout of FIG. 19 orother layouts may be similarly used. For ease of reference, a column isreferred to as being in the y-direction in this example. Thus, bit cellsC1 and C2 are in a first column, and bit cells C3 and C4 are in a secondcolumn. As depicted, adjacent cells in the array are mirror images alonga border between the adjacent cells.

Each active area in a bit cell extends through multiple bit cells in acolumn. In an embodiment, each active area in a bit cell extends throughall of the bit cells in a column. In other embodiments, each active areaextends through less than all of the bit cells in the column. In FIG.20, the active area for transistors IS2 and PU2 in bit cell C1 extendsthrough bit cell C2 as the active area for transistors PU2 and IS2. Inthis configuration, the drains of the isolation transistors IS2 inadjacent bit cells C1 and C2 are coupled together (such as depicted inFIG. 18 between bit cells C2 and C3) because the drains share a commonnode along the same active area. Similarly, the active area fortransistors IS2 and PU2 in bit cell C3 extends through bit cell C4 asthe active area for transistors PU2 and IS2. Although not illustrated,each of the active areas of isolation transistors IS1 in each bit cellextends into an adjacent bit cell to be the active area of respectiveisolation transistors IS1 in the adjacent bit cell, thereby forming thecoupling between isolation transistors IS1 in adjacent bit cells, asdepicted in FIG. 18.

In operation, the bit cells in FIGS. 16 through 20 generally operate asa conventional two port SRAM cell operates. When write operations areperformed on a write port, pass-gate transistors PG1 and PG2 are turnedon using the write word line WWL, and a voltage to which the write bitline WBL and the complementary write bit line WBLB are driven will besensed through the pass-gate transistors PG1 and PG2 by thecross-coupled transistors PU1, PU2, PD1, and PD2. The cross-coupledtransistors PU1, PU2, PD1, and PD2 drive the storage nodes N1 and N2 toa high or low state based on the sensing (with the storage nodes N1 andN2 being complementary of each other). The data is thus written into thebit cell through bit lines WBL and WBLB. Conversely, when readoperations are performed through a read port, read pass-gate transistorRPG is turned on by the read word line RWL, and the data is read ontothe read bit line RBL through the transistor RPG.

As previously discussed with respect to FIGS. 1 through 5, the isolationtransistors IS1 and IS2 in FIGS. 16 through 20 may have a negligibleeffect on the operation of the bit cell. During operation, currentgenerally may not flow through the isolation transistors IS1 and IS2,and in some instances, a small amount of leakage may flow through theisolation transistor IS1 or IS2 when the voltage at the node isswitched, e.g., from low to high and vice versa. With fast switchingtimes and/or low voltages, the leakage current can be very small andnegligible.

By having the bit cells in the configuration in FIG. 20, active areascan be more uniformly spaced and can uniformly extend throughout anarray of bit cells, as discussed with reference to FIG. 5. Further, theactive areas can extend longitudinally across multiple bit cells withoutbeing interrupted by an isolation area.

FIGS. 21A and 21B illustrate an example of metallization patterns forthe bit cell layouts in FIG. 19. The dashed rectangles in these figuresindicate a boundary of the bit cell that corresponds to the boundaryshown in FIGS. 19. These are an example pattern, and a person havingordinary skill in the art will readily appreciate various modificationsto the example or different patterns that are contemplated within thescope of embodiments.

FIG. 21A is a first metallization pattern M1 in a first inter-metaldielectric layer IMD1, and FIG. 21B is a second metallization pattern M2in a second inter-metal dielectric layer IMD2 overlying the firstinter-metal dielectric layer IMD1. In FIG. 21A, the first metallizationpattern M1 includes a first ground trace Vss1, a write bit line traceWBL, a power trace Vdd, a complementary write bit line trace WBLB, asecond ground trace Vss2, and a read bit line trace RBL, each traceextending longitudinally in the y-direction, which in the context ofFIG. 20 is along a column. The first metallization pattern M1 furtherincludes three landing pads L1, L2, and L3. Although not expresslyshown, a person having ordinary skill in the art will readily understandthat vias extend below and from the first metallization pattern M1 tothe respective contacts shown in the bit cell layout in FIG. 19. In FIG.21B, the second metallization pattern M2 includes a write word linetrace WWL and a read word line trace RWL, each extending longitudinallyin the x-direction, which in the context of FIG. 20 is along a row. ViasV1, V2, and V3 extend below and from the second metallization pattern M2to respective landing pads L1, L2, and L3 in the first metallizationpattern M1. Each of the traces in FIGS. 21A and 21B can transversemultiple cells in the respective directions in which the traceslongitudinally extend.

FIG. 22 illustrates a memory layout according to an embodiment. Thememory layout comprises a first array of bit cells A1 and a second arrayof bit cells A2. The arrays A1 and A2 are each surrounded by dummy bitcells. For example, a first dummy column DC1 and a second dummy columnDC2 are on opposite horizontal sides of each array A1 and A2. A firstdummy row DR1 and a second dummy row DR2 are on opposite vertical sidesof array A1, and the second dummy row DR2 and a third dummy row DR3 areon opposite vertical sides of array A2. Various patterns of dummy rowsor columns can be dispersed throughout a memory layout. Dummy bit cellsin this configuration can allow edge effects, such as from lithographypatterning, to be absorbed by the dummy cells rather than by operationalmemory bit cells.

FIGS. 23 through 31 illustrate a method of forming a memory arraycomprising finFETs according to an embodiment. Although the method isdiscussed specifically with regard to the bit cells of FIGS. 4A and 5and the metallization patterns of FIGS. 7A and 7B, a person havingordinary skill in the art will readily appreciate the applicability andany modifications for forming other bit cells and/or metallizationpatterns. Also, a person having ordinary skill in the art will readilyunderstand the applicability of embodiments using planar transistors.Further, although the method is discussed in a particular order, otherembodiments may be performed in any logical order.

FIGS. 23 through 25 illustrate process steps in a cross section view,for example, along an x-z plane in a bit cell. In FIG. 23, a substrate10 is provided, such as a semiconductor substrate, a semiconductor oninsulator (SOI) substrate, or the like. In an embodiment, the substrateis a bulk silicon substrate. The substrate 10 may be doped to form wellsof appropriate dopant types and concentrations in areas of the substrate10 where finFETs will be formed.

In FIG. 24, the substrate 10 is etched to form fins 12. The fins 12 maybe formed by depositing a mask layer over the substrate 10 anddepositing a photoresist over the mask layer. The photoresist can bepatterned into the fin pattern by appropriate exposure to light. The finpattern is transferred to the mask layer by an etch, and the fin patternis transferred from the mask layer to the substrate 10 by an etch. If anSOI substrate is used, the etch may be to a depth to the insulator or toa depth above or below the insulator.

In FIG. 25, isolation structures 14 are formed between fins 12. Aninsulating layer, such as a high density plasma oxide, can be depositedover the substrate 10 and fins 12 and etched back to form the isolationstructures 14, according to acceptable deposition and lithographytechniques. A person having ordinary skill in the art will readilyunderstand other methods by which the fins 12 can be formed, and thesemethods are contemplated by embodiments. For example, an insulatinglayer can be formed over a substrate, trenches can be formed in theinsulating layer exposing the substrate, and fins can be epitaxiallygrown from the substrate through the fins.

FIG. 26 is a layout view, for example, an x-y plane, of the fins 12after the processing discussed with regard to FIG. 25. The layoutcorresponds, for example, to bit cells C1 and C2 in FIG. 5, although thelayout can equally apply to other bit cells in an array. Dashed line A-Arepresents the cross section of the fin 12 illustrated in FIGS. 27through 31.

In FIG. 27, gate structures 16 are formed over the fin 12. The gatestructures 16 may each include a gate dielectric, a gate electrode, anddielectric sidewall spacers. The gate dielectric and gate electrode canbe formed by depositing a dielectric layer and an electrode layersequentially on the substrate 10 (or fins 12) and etching the layersinto the patterned gate dielectric and gate electrode. A dielectriclayer can then be conformally deposited and etched to form thedielectric sidewall spacers. A person having ordinary skill in the artwill readily understand acceptable materials and processes for formingthese components.

In FIG. 28, raised source/drain regions 18 are formed. The raisedsource/drain regions 18 can be formed by etching openings in thesource/drain regions of the fin 12 and epitaxially growing the raisedsource/drain regions 18. The raise source/drain regions 18 can comprise,for example, silicon germanium (SiGe) for a p-type transistor or siliconcarbon (SiC) for an n-type transistor, although other materials may beused. The raise source/drain regions 18 can be appropriately doped afterthe epitaxial growth or can be in situ doped during the growth. Afterthe raised source/drain regions 18 are formed, an additional sidewallspacer 20 can be formed on the sidewalls of the gate structures 16. Thespacers 20 can be formed by conformally depositing a dielectric layerover the substrate 10 and etching.

In FIG. 29, a first interlayer dielectric ILD1 is formed over thesubstrate 10 and fin 12. The interlayer dielectric ILD1 is planarized toa top surface of the gate structures 16, such as by a chemicalmechanical polish (CMP). Contact openings are etched to the raisedsource/drain regions 18, and a conductive material is deposited in thecontact openings and over the interlayer dielectric ILD1. The conductivematerial is planarized to a top surface of the interlayer dielectricILD1, such as by a chemical mechanical polish (CMP), leaving conductivematerial in the contact openings to form contacts 22. The etching anddeposition can be by any acceptable etching and deposition process,respectively. The contacts 22 can comprise any acceptable conductivematerial, such as a doped semiconductor or metal, such as copper,titanium, tungsten, aluminum, or the like. Further, a barrier layer maybe formed between the conductive material and the interlayer dielectricILD1, and an etch stop layer may be formed over the substrate 10 underthe interlayer dielectric layer ILD1. A person having ordinary skill inthe art will readily understand appropriate processes and materials usedfor forming these components.

In FIG. 30, a second interlayer dielectric ILD2 is formed over the firstinterlayer dielectric ILD1, and butted contacts 26 and contacts 24 areformed in the second interlayer dielectric ILD2. The process andmaterials for forming these components is the same as or similar tothose discussed with regard to FIG. 29, which would be readilyappreciated by a person having ordinary skill in the art. Further,although not expressly depicted, an etch stop layer may be between thefirst interlayer dielectric ILD1 and the second interlayer dielectricILD2.

In other embodiments, one interlayer dielectric layer can take the placeof the two interlayer dielectrics ILD1 and ILD2, and the contacts 22,24, and 26 can have openings formed from a single etch step and singledeposition step.

In FIG. 31, a first intermetal dielectric layer IMD1 is formed over thefirst interlayer dielectric layer ILD1, and a first metallization layerM1, illustrated by power trace Vdd, is formed in the first inter-metaldielectric layer IMD1. Vias 28 are formed in the first inter-metaldielectric layer IMD1 to the contacts 24 in the interlayer dielectriclayer ILD2. A second intermetal dielectric layer IMD2 is formed over thefirst inter-metal dielectric layer IMD1, and a second metallizationlayer M2, illustrated by word line traces WL, is formed in the secondinter-metal dielectric layer IMD2. Vias (not depicted) are formed in thesecond inter-metal dielectric layer IMD2 to the landing pads in thefirst metallization layer M2. The inter-metal dielectric layers IMD1 andIMD2 can be formed by acceptable deposition techniques and withappropriate dielectric materials. The metallization layers M1 and M2 andvias can be formed using a single or dual damascene process and withappropriate materials, such as a metal, such as copper, titanium,tungsten, aluminum, or the like. An etch stop layer can be formedbetween the interlayer dielectric layer ILD2 and the inter-metaldielectric layer IMD1 and between the inter-metal dielectric layers IMD1and IMD2. Further, barrier layers can be formed between the inter-metaldielectric layer and the conductive material of the metal patterns andvias. Further metallization layers and dielectric layers can be formedover the second inter-metal dielectric layer IMD2.

The cross section view of FIG. 31 corresponds to a structure with thelayout in FIGS. 4A and 5 and the metallization patterns in FIGS. 7A and7B. A person having ordinary skill in the art will readily understandthe correspondence of these figures to the two bit cells C1 and C2 inFIG. 31.

A first embodiment is a memory cell comprising a first pull-uptransistor, a first pull-down transistor, a second pull-up transistor, asecond pull-down transistor, a first pass-gate transistor, a secondpass-gate transistor, a first isolation transistor, and a secondisolation transistor. A drain of the first pull-up transistor iselectrically coupled to a drain of the first pull-down transistor at afirst node. A drain of the second pull-up transistor is electricallycoupled to a drain of the second pull-down transistor at a second node.A gate of the second pull-up transistor and a gate of the secondpull-down transistor are electrically coupled to the first node, and agate of the first pull-up transistor and a gate of the first pull-downtransistor are electrically coupled to the second node. The firstpass-gate transistor is electrically coupled to the first node, and thesecond pass-gate transistor is electrically coupled to the second node.The first isolation transistor is electrically coupled to the firstnode, and the second isolation transistor is electrically coupled to thesecond node.

Another embodiment is a memory array. The memory array comprises a firstmemory cell and a second memory cell. The first memory cell comprises afirst set of transistors, and the second memory cell comprises a secondset of transistors. Each of the first and second set of transistorscomprises a first pull-up transistor, a first pull-down transistor, asecond pull-up transistor, a second pull-down transistor, a firstpass-gate transistor, a second pass-gate transistor, a first isolationtransistor, and a second isolation transistor. An active area of eachone transistor of the first set of transistors extends beyond a boundaryof the first memory cell and into the second memory cell, and theboundary is shared by the first memory cell and the second memory cell.

A further embodiment is a method for forming a memory array. The methodcomprises forming a first fin, a second fin, a third fin, and a fourthfin; and forming a first pull-up transistor, a second pull-uptransistor, a first pull-down transistor, a second pull-down transistor,a first pass-gate transistor, a second pass-gate transistor, a firstisolation transistor, and a second isolation transistor in each of afirst memory cell area and a second memory cell area. Each of the firstfin, second fin, third fin, and fourth fin extends across the firstmemory cell area and the second memory cell area. The first pull-uptransistor and the first isolation transistor of each of the firstmemory cell area and the second memory cell area comprise the first fin.The second pull-up transistor and the second isolation transistor ofeach of the first memory cell area and the second memory cell areacomprise the second fin. The first pass-gate transistor and the firstpull-down transistor of each of the first memory cell area and thesecond memory cell area comprise the third fin. The second pass-gatetransistor and the second pull-down transistor of each of the firstmemory cell area and the second memory cell area comprisw the fourthfin.

Although the present embodiments and their advantages have beendescribed in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the disclosure as defined by the appendedclaims. Moreover, the scope of the present application is not intendedto be limited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed, that perform substantially the same function orachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized according to the present disclosure.Accordingly, the appended claims are intended to include within theirscope such processes, machines, manufacture, compositions of matter,means, methods, or steps.

What is claimed is:
 1. A memory array comprising: a first active area, asecond active area, a third active area, and a fourth active area eachtraversing a first memory cell area and a second memory cell area, thefirst memory cell area being adjacent to the second memory cell area;wherein in the first memory cell area: the first active area is acomponent of a first pull-down transistor, the second active area is acomponent of a first pull-up transistor, a drain of the first pull-uptransistor being electrically coupled to a drain of the first pull-downtransistor at a first node, the third active area is a component of afirst isolation transistor and a second pull-up transistor, and thefourth active area is a component of a second pull-down transistor, adrain of the second pull-up transistor being electrically coupled to adrain of the second pull-down transistor at a second node, a gate of thesecond pull-up transistor and a gate of the second pull-down transistorbeing electrically coupled to the first node, a gate of the firstpull-up transistor and a gate of the first pull-down transistor beingelectrically coupled to the second node; wherein in the second memorycell area: the first active area is a component of a third pull-downtransistor, the second active area is a component of a third pull-uptransistor, a drain of the third pull-up transistor being electricallycoupled to a drain of the third pull-down transistor at a third node,the third active area is a component of a second isolation transistorand a fourth pull-up transistor, and the fourth active area is acomponent of a fourth pull-down transistor, a drain of the fourthpull-up transistor being electrically coupled to a drain of the fourthpull-down transistor at a fourth node, a gate of the fourth pull-uptransistor and a gate of the fourth pull-down transistor beingelectrically coupled to the third node, a gate of the third pull-uptransistor and a gate of the third pull-down transistor beingelectrically coupled to the fourth node; and wherein the first isolationtransistor and the second isolation transistor have a sharedsource/drain region at a boundary between the first memory cell area andthe second memory cell area, the shared source/drain region not having acontact directly coupled thereto.
 2. The memory array of claim 1,wherein: in the first memory cell area: the first active area is acomponent of a first pass-gate transistor, and the fourth active area isa component of a second pass-gate transistor, and in the second memorycell area: the first active area is a component of a third pass-gatetransistor, and the fourth active area is a component of a fourthpass-gate transistor.
 3. The memory array of claim 1 further comprisinga fifth active area and a sixth active area each traversing the firstmemory cell area and the second memory cell area, wherein in the firstmemory cell area: the fifth active area is a further component of thefirst pull-down transistor, and the sixth active area is a furthercomponent of the second pull-down transistor, and wherein in the secondmemory cell area: the fifth active area is a further component of thethird pull-down transistor, and the sixth active area is a furthercomponent of the fourth pull-down transistor.
 4. The memory array ofclaim 1, wherein each of the first active area, the second active area,the third active area, and the fourth active area comprises a fin activearea.
 5. The memory array of claim 1 further comprising a firstmetallization layer over the active areas and a second metallizationlayer over the first metallization layer, one of the first metallizationlayer or the second metallization layer comprising a bit line tracetraversing the first memory cell area and the second memory cell area,the other of the first metallization layer or the second metallizationlayer comprising a first word line trace extending across the firstmemory cell area at a direction that intersects the bit line trace and asecond word line trace extending across the second memory cell area at adirection that intersects the bit line trace.
 6. The memory array ofclaim 5, wherein the one of the first metallization layer or the secondmetallization layer further comprises a power trace traversing the firstmemory cell area and the second memory cell area, and the other of thefirst metallization layer or the second metallization layer furthercomprises a first ground trace extending across the first memory cellarea at a direction that intersects the bit line trace and a secondground trace extending across the second memory cell area at a directionthat intersects the bit line trace.
 7. The memory array of claim 5,wherein the one of the first metallization layer or the secondmetallization layer further comprises a power trace traversing the firstmemory cell area and the second memory cell area, and further comprisesa ground trace traversing the first memory cell area and the secondmemory cell area.
 8. The memory array of claim 5, wherein the one of thefirst metallization layer or the second metallization layer furthercomprises (i) a power trace traversing the first memory cell area andthe second memory cell area, (ii) a first ground trace traversing thefirst memory cell area and the second memory cell area, and (iii) asecond ground trace traversing the first memory cell area and the secondmemory cell area, and the other of the first metallization layer or thesecond metallization layer further comprises a ground mesh trace, afirst via electrically coupling the ground mesh trace to the firstground trace, and a second via electrically coupling the ground meshtrace to the second ground trace.
 9. The memory array of claim 1,further comprising a fifth active area and a sixth active area eachtraversing the first memory cell area and the second memory cell area,wherein in the first memory cell area: the first active area is acomponent of a first pass-gate transistor, the fourth active area is acomponent of a second pass-gate transistor, the fifth active area is acomponent of a third pass-gate transistor, and the sixth active area isa component of a fourth pass-gate transistor, and wherein in the secondmemory cell area: the first active area is a component of a fifthpass-gate transistor, the fourth active area is a component of a sixthpass-gate transistor, the fifth active area is a component of a seventhpass-gate transistor, and the sixth active area is a component of aeighth pass-gate transistor.
 10. The memory array of claim 1, furthercomprising a fifth active area traversing the first memory cell area andthe second memory cell area, wherein in the first memory cell area: thefifth active area is a component of a first read pass-gate transistorand a first read pull-down transistor, and wherein in the second memorycell area: the fifth active area is a component of a second readpass-gate transistor and a second read pull-down transistor.
 11. Amemory array comprising: a first static random access memory (SRAM) cellarea on a substrate; and a second SRAM cell area on the substrate, thefirst SRAM cell area adjoining the second SRAM cell area at a boundary,a fin active area being in each of the first SRAM cell area and thesecond SRAM cell area and extending across the boundary, the fin activearea being (i) a component of a first isolation transistor in the firstSRAM cell area, (ii) a component of a first operational transistor inthe first SRAM cell area, (iii) a component of a second isolationtransistor in the second SRAM cell area, and (iv) a component of asecond operational transistor in the second SRAM cell area.
 12. Thememory array of claim 11, wherein each of the first SRAM cell area andthe second SRAM cell area comprises: a first pull-down transistor, afirst pull-up transistor, a drain of the first pull-up transistor beingelectrically coupled to a drain of the first pull-down transistor at afirst node, the first pull-up transistor in the first SRAM cell areabeing the first operational transistor, and the first pull-up transistorin the second SRAM cell area being the second operational transistor, asecond pull-up transistor, and a second pull-down transistor, a drain ofthe second pull-up transistor being electrically coupled to a drain ofthe second pull-down transistor at a second node, a gate of the secondpull-up transistor and a gate of the second pull-down transistor beingelectrically coupled to the first node, a gate of the first pull-uptransistor and a gate of the first pull-down transistor beingelectrically coupled to the second node.
 13. The memory array of claim11, wherein each of the first SRAM cell area and the second SRAM cellarea comprises a double pitch transistor.
 14. The memory array of claim11, wherein each of the first SRAM cell area and the second SRAM cellarea comprises a dual port SRAM cell.
 15. The memory array of claim 11,wherein each of the first SRAM cell area and the second SRAM cell areacomprises a two-port SRAM cell.
 16. A method comprising: forming a finactive area on a substrate, the fin active area extending across aboundary of a first static random access memory (SRAM) cell area into asecond SRAM cell area; forming a first gate structure over the finactive area in the first SRAM cell area proximate the boundary and asecond gate structure over the fin active area in the second SRAM cellarea proximate the boundary; forming a dielectric layer over the finactive area, the first gate structure, and the second gate structure;and forming a first contact through the dielectric layer to asource/drain region of the fin active area in the first SRAM cell areaand a second contact through the dielectric layer to a source/drainregion of the fin active area in the second SRAM cell area, the firstcontact being on an opposite side of the first gate structure from theboundary, the second contact being on an opposite side of the secondgate structure from the boundary, no contact being formed to a region ofthe fin active area at the boundary between the first gate structure andthe second gate structure.
 17. The method of claim 16 furthercomprising: forming a first metallization layer over the substrate; andforming a second metallization layer over the first metallization layer,one of the first metallization layer or the second metallization layercomprising a bit line trace traversing the first SRAM cell area and thesecond SRAM cell area, the other of the first metallization layer or thesecond metallization layer comprising a first word line trace extendingacross the first SRAM cell area at a direction that intersects the bitline trace and a second word line trace extending across the second SRAMcell area at a direction that intersects the bit line trace.
 18. Themethod of claim 17, wherein the one of the first metallization layer orthe second metallization layer further comprises a power tracetraversing the first SRAM cell area and the second SRAM cell area, andthe other of the first metallization layer or the second metallizationlayer further comprises a first ground trace extending across the firstSRAM cell area at a direction that intersects the bit line trace and asecond ground trace extending across the second SRAM cell area at adirection that intersects the bit line trace.
 19. The method of claim17, wherein the one of the first metallization layer or the secondmetallization layer further comprises a power trace traversing the firstSRAM cell area and the second SRAM cell area, and further comprises aground trace traversing the first SRAM cell area and the second SRAMcell area.
 20. The method of claim 17, wherein the one of the firstmetallization layer or the second metallization layer further comprises(i) a power trace traversing the first SRAM cell area and the secondSRAM cell area, (ii) a first ground trace traversing the first SRAM cellarea and the second SRAM cell area, and (iii) a second ground tracetraversing the first SRAM cell area and the second SRAM cell area, andthe other of the first metallization layer or the second metallizationlayer further comprises a ground mesh trace, a first via electricallycoupling the ground mesh trace to the first ground trace, and a secondvia electrically coupling the ground mesh trace to the second groundtrace.
 21. A memory array comprising: a first active area, a secondactive area, a third active area, and a fourth active area eachtraversing a first memory cell area and a second memory cell area, thefirst memory cell area being adjacent to the second memory cell area;wherein in the first memory cell area: the first active area is acomponent of a first pull-down transistor, the second active area is acomponent of a first pull-up transistor, a drain of the first pull-uptransistor being electrically coupled to a drain of the first pull-downtransistor at a first node, the third active area is a component of afirst isolation transistor and a second pull-up transistor, and thefourth active area is a component of a second pull-down transistor, adrain of the second pull-up transistor being electrically coupled to adrain of the second pull-down transistor at a second node, a gate of thesecond pull-up transistor and a gate of the second pull-down transistorbeing electrically coupled to the first node, a gate of the firstpull-up transistor and a gate of the first pull-down transistor beingelectrically coupled to the second node; wherein in the second memorycell area: the first active area is a component of a third pull-downtransistor, the second active area is a component of a third pull-uptransistor, a drain of the third pull-up transistor being electricallycoupled to a drain of the third pull-down transistor at a third node,the third active area is a component of a second isolation transistorand a fourth pull-up transistor, and the fourth active area is acomponent of a fourth pull-down transistor, a drain of the fourthpull-up transistor being electrically coupled to a drain of the fourthpull-down transistor at a fourth node, a gate of the fourth pull-uptransistor and a gate of the fourth pull-down transistor beingelectrically coupled to the third node, a gate of the third pull-uptransistor and a gate of the third pull-down transistor beingelectrically coupled to the fourth node; and wherein the first isolationtransistor and the second isolation transistor have a sharedsource/drain region at a boundary between the first memory cell area andthe second memory cell area.
 22. The memory array of claim 21, wherein:in the first memory cell area: the first active area is a component of afirst pass-gate transistor, and the fourth active area is a component ofa second pass-gate transistor, and in the second memory cell area: thefirst active area is a component of a third pass-gate transistor, andthe fourth active area is a component of a fourth pass-gate transistor.23. The memory array of claim 21 further comprising a fifth active areaand a sixth active area each traversing the first memory cell area andthe second memory cell area, wherein in the first memory cell area: thefifth active area is a further component of the first pull-downtransistor, and the sixth active area is a further component of thesecond pull-down transistor, and wherein in the second memory cell area:the fifth active area is a further component of the third pull-downtransistor, and the sixth active area is a further component of thefourth pull-down transistor.
 24. The memory array of claim 21, whereineach of the first active area, the second active area, the third activearea, and the fourth active area comprises a fin active area.
 25. Thememory array of claim 21 further comprising a first metallization layerover the active areas and a second metallization layer over the firstmetallization layer, one of the first metallization layer or the secondmetallization layer comprising a bit line trace traversing the firstmemory cell area and the second memory cell area, the other of the firstmetallization layer or the second metallization layer comprising a firstword line trace extending across the first memory cell area at adirection that intersects the bit line trace and a second word linetrace extending across the second memory cell area at a direction thatintersects the bit line trace.
 26. The memory array of claim 25, whereinthe one of the first metallization layer or the second metallizationlayer further comprises a power trace traversing the first memory cellarea and the second memory cell area, and the other of the firstmetallization layer or the second metallization layer further comprisesa first ground trace extending across the first memory cell area at adirection that intersects the bit line trace and a second ground traceextending across the second memory cell area at a direction thatintersects the bit line trace.
 27. The memory array of claim 25, whereinthe one of the first metallization layer or the second metallizationlayer further comprises a power trace traversing the first memory cellarea and the second memory cell area, and further comprises a groundtrace traversing the first memory cell area and the second memory cellarea.
 28. The memory array of claim 25, wherein the one of the firstmetallization layer or the second metallization layer further comprises(i) a power trace traversing the first memory cell area and the secondmemory cell area, (ii) a first ground trace traversing the first memorycell area and the second memory cell area, and (iii) a second groundtrace traversing the first memory cell area and the second memory cellarea, and the other of the first metallization layer or the secondmetallization layer further comprises a ground mesh trace, a first viaelectrically coupling the ground mesh trace to the first ground trace,and a second via electrically coupling the ground mesh trace to thesecond ground trace.
 29. The memory array of claim 21, furthercomprising a fifth active area and a sixth active area each traversingthe first memory cell area and the second memory cell area, wherein inthe first memory cell area: the first active area is a component of afirst pass-gate transistor, the fourth active area is a component of asecond pass-gate transistor, the fifth active area is a component of athird pass-gate transistor, and the sixth active area is a component ofa fourth pass-gate transistor, and wherein in the second memory cellarea: the first active area is a component of a fifth pass-gatetransistor, the fourth active area is a component of a sixth pass-gatetransistor, the fifth active area is a component of a seventh pass-gatetransistor, and the sixth active area is a component of a eighthpass-gate transistor.
 30. The memory array of claim 21, furthercomprising a fifth active area traversing the first memory cell area andthe second memory cell area, wherein in the first memory cell area: thefifth active area is a component of a first read pass-gate transistorand a first read pull-down transistor, and wherein in the second memorycell area: the fifth active area is a component of a second readpass-gate transistor and a second read pull-down transistor.
 31. Amemory cell comprising: a first pull-up transistor and a first pull-downtransistor, a drain of the first pull-up transistor being electricallycoupled to a drain of the first pull-down transistor at a first node; asecond pull-up transistor and a second pull-down transistor, a drain ofthe second pull-up transistor being electrically coupled to a drain ofthe second pull-down transistor at a second node, a gate of the secondpull-up transistor and a gate of the second pull-down transistor beingelectrically coupled to the first node, a gate of the first pull-uptransistor and a gate of the first pull-down transistor beingelectrically coupled to the second node; a first pass-gate transistorelectrically coupled to the first node; a second pass-gate transistorelectrically coupled to the second node; a first isolation transistorelectrically coupled to the first node; and a second isolationtransistor electrically coupled to the second node, wherein the firstisolation transistor is configured to have a source and a gate coupledto the first node, and the second isolation transistor is configured tohave a source and a gate coupled to the second node.
 32. The memory cellof claim 31, wherein a drain of the first isolation transistor isfloating.
 33. The memory cell of claim 32, wherein a bit line (BL) orpower voltage (VDD) is formed over the drain of the first isolationtransistor.
 34. The memory cell of claim 32, wherein the drain of thefirst isolation transistor is sandwiched between a bit line (BL) and apower voltage (VDD).
 35. The memory cell of claim 31, wherein a drain ofthe second isolation transistor is floating.
 36. The memory cell ofclaim 35, wherein a complementary bit line (BLB) or a power voltage(VDD) is formed over the drain of the second isolation transistor. 37.The memory cell of claim 35, wherein the drain of the second isolationtransistor is sandwiched between a complementary bit line (BLB) and apower voltage (VDD).
 38. The memory cell of claim 31, wherein a wordline (WL) is formed over the first and second isolation transistors. 39.The memory cell of claim 31, wherein a drain of the first isolationtransistor is formed at a first side of a word line (WL), a drain of thesecond isolation transistor is formed at a second side of the WL. 40.The memory cell of claim 31, wherein a first word line (AWL) or a secondword line (BWL) is formed over a drain of the first isolationtransistor.
 41. The memory cell of claim 31, wherein a first word line(AWL) or a second word line (BWL) is formed over a drain of the secondisolation transistor.
 42. The memory cell of claim 31, wherein a writeword line (WWL) or a read word line (RWL) is formed over a drain of thefirst isolation transistor.
 43. The memory cell of claim 31, wherein awrite word line (WWL) or a read word line (RWL) is formed over a drainof the second isolation transistor.